1. Field of the Invention
The present invention relates to a flip chip semiconductor integrated circuit, and more particularly to a layout structure of a flip chip semiconductor integrated circuit.
2. Description of the Prior Art
A flip chip semiconductor integrated circuit (abbreviated to FC IC, hereinafter) has a feature of connecting a package and a chip with each other through a spherical solder ball instead of conventional wire bonding or tape automated bonding (TAB), and a structure, in which the solder ball as a pad can be arranged on a full surface of the chip.
Hereinafter, a first conventional example will be described with reference to FIGS. 26 to 28. FIG. 26 is a plan view showing a layout structure of an FC IC according to the first conventional example. In FIG. 26, the FC IC is seen through from above. The FC IC of the first conventional example has a structure, in which a plurality of input/output buffers (referred to as I/O buffers, hereinafter) 101 are one-dimensionally arranged on four sides of a chip 351, an internal cell region 3152 is provided to be surrounded with a row of the I/O buffers 101 arranged on each side, and a solder ball is arranged on a full surface of the chip. In FIG. 26, a reference numeral 121 denotes an internal cell, and 2535 a RAM.
FIG. 27 is a partially expanded plan view of the FC IC of FIG. 26. The plurality of I/O buffers 101 arrayed in an X direction (or Y direction), and solder balls 113, 114, 115, 1033 and 1134 arranged in a Y direction (or X direction) are interconnected by drawer wires 3216, 3217 and 3218.
The solder balls are classified as an I/O buffer GND solder ball 113, an I/O buffer power supply solder ball 114, a signal solder ball 115, an internal cell GND solder ball 1033, and an internal cell power supply solder ball 1134. The drawer wires are classified as an I/O buffer GND drawer wire 3216, an I/O buffer power supply drawer wire 3217, and a signal drawer wire 3218.
A signal of the I/O buffer 101 is transmitted through signal drawer wire 3218 to the signal solder ball 115 arranged an upper part in a region of the I/O buffer 101, or on an upper part outside the region. When the plurality of I/O buffers 101 are arranged side by side, the I/O buffer GND wires 107 of the respective I/O buffers 101 are connected to each other, and the I/O buffer power supply wires 108 are connected to each other.
Then, the I/O buffer GND wire 107 is connected through the I/O buffer GND drawer wire 3216 to the I/O buffer GND solder ball 113 arranged on the upper part in the region of the I/O buffer 101 or on the upper part outside the region. The I/O buffer power supply wire 108 is connected through the I/O buffer power supply drawer wire 3217 to the I/O buffer power supply solder ball 114 arranged on the upper part in the region of the I/O buffer 101 or on the upper part outside the region. Accordingly, a power supply potential and a GND potential are supplied from the I/O buffer power supply solder ball 114 and the I/O buffer GND solder ball 113 to the I/O buffer 101.
FIG. 28 is a sectional view of the FC IC shown in FIG. 27, specifically showing a structure of connection between the signal solder ball 115 and the I/O buffer 101. In FIG. 28, a reference numeral 300 denotes an insulating film. The I/O buffer 101 and the internal cell 121 are arranged on a substrate 255.
An I/O buffer internal signal terminal 209 of the I/O buffer 101, and an internal cell signal terminal 232 of the internal cell 121 are connected to each other through a lower inter-signal wire 229. Similarly, internal cell signal terminals 232 of different internal cells 121 are connected to each other through the inter-signal wire 229. An I/O buffer signal terminal 112 is connected to the signal solder ball 115 through the signal drawer wire 3218, a through-hole 3157, and an upper barrier metal 158.
The FC IC of the first conventional example shown in FIGS. 26 to 28 has a feature that it also functions as an FC IC substrate, where one not-shown pad is arranged outside the I/O buffer 101, and a peripheral IC connecting a package with a chip through a bonding wire or TAB, and the solder balls 113, 114, 115, 1033 and 1134 are arrayed on a full chip surface.
Next, a second conventional example is described with reference to FIGS. 29 and 30. FIG. 29 is a plan view showing a layout structure of an FC IC according to the second conventional example. The second conventional example was presented by an applicant of the present invention in Japanese Patent Application No. 2000-050240. In FIG. 29, the FC IC is seen through from above.
The second conventional example has a structure, in which combinations of an I/O buffer 101, an I/O buffer GND solder ball 113, an I/O buffer power supply solder ball 114, a signal solder ball 115, an I/O buffer GND drawer wire 3216, an I/O buffer power supply drawer wire 3217, and a signal drawer wire 3218 are collected in a group 3453, and this group 3453 is housed in a region of an integral multiple of a section definition 3454.
A signal terminal 112 of the I/O buffer 101 is connected to the solder ball 115 through the signal drawer wire 3218, a not-shown through-hole, and an upper barrier metal 158. A GND terminal 110 of the I/O buffer 101 is connect t o the I/O buffer GND solder ball 113 through the I/O buffer GND drawer wire 3216, the not-shown through-hole, and the upper barrier metal 158. A power supply terminal 111 of the I/O buffer 101 is connected to the I/O buffer power supply solder ball 114 through the I/O buffer power supply drawer wire 3217, the not-shown through-hole, and the upper barrier metal 158. Accordingly, a GND potential and a power supply potential of the I/O buffer are supplied from the I/O buffer GND solder ball 113 and the I/O buffer power supply solder ball 114 installed nearby.
FIG. 30 is a chip layout plan view, in which each group 3453 of FIG. 29 is arranged on a chip 351, and only double crossed GND wire and power supply wire 3519 of the I/O buffer 101 are shown. The drawing specifically shows a state where the double crossed GND wire and power supply wire arranged adjacently to each other are interconnected in the group 3453. The second conventional example shown in FIGS. 29 and 30 has a feature that each group 3453 can be freely arranged on the chip 351.
Designing of a cell base IC can be generally classified into a product designing process for specifically designing an IC by realizing a circuit for each product such as arrangement of the I/O buffer 101 and the internal cell 121 or wiring between the signal terminals, and a base designing process for preparing a database necessary for automating produce designing, such as solder ball arrangement, designation of the I/O buffer 101 and the internal cell region 3152, power supplying wiring, circuits thereof, or layout designing.
For designing of each product, an automatic designing tool or the like is used based on the database prepared by the base designing. In designing of each product, if a problem regarding the base designing occurs, the number of backtracking man-hours is large, increasing designing TAT (number of process days). Accordingly, occurrence of problems in designing each product is prevented by verifying problems to be expected in the base designing, such as a potential reduction in the internal cell region.
Next, a conventional method of designing an FC IC b product is described with reference to FIG. 31. FIG. 31 is a flowchart showing the conventional method of designing an FC IC product. First, as designing information for each product, a design rule (geometric design rule) 1601 containing information such as a wiring pitch or the like, package information 1602 containing information regarding coordinates of the solder balls 113 to 115, 1033 and 1134, a solder ball pitch or the like, and a customer specification 1603 containing information regarding function describing data, pin arrangement, the number of pins or the like are prepared beforehand.
Subsequently, a designer carries out simulation of a function level by using a simulator or the like based on the customer specification to check an the operation of the function level (step 1605), and then carries out logic synthesis (step 1606) to generate circuit information 1607, which includes circuit blocks of the I/O buffer 101, the internal cell 121 and the like as components.
Then, in step 3607, base designing is carried out based on the design rule 1601, the package information 1602, the customer specification 1603, and the circuit information 1607, and a base database 1608 containing information regarding arrangement of the I/O buffer 101, arrangement of the solder ball or the like is prepared. This step 3607 is specific to the FC IC, and its detail will be described with reference to FIG. 32.
Then, the designer roughly arranges the I/O buffer 101, the internal cell 121 including a RAM or a macro, the power supply wire and the like based on the circuit information 1607 and the base database 1608 (step 1609). Then, the designer temporarily decides a wiring length between the circuit blocks based on the base database 1608 by using a computer or the like, and carries out temporary wiring length simulation by using its electric load (step 1610).
Here, the designer checks a result of the temporary wiring length simulation, and checks whether the IC is operating as expected or not (step 1611). If there is a problem, the rough arrangement made in step 1609 is changed (step 1613), and then the process returns to step 1610.
If there are no problems found in step 1611, the designer establishes the circuit arrangement of the entire IC including other circuits added to the roughly arranged circuit blocks by the computer, and automatic wiring is carried out between the circuits (step 1612). Here, since real wiring lengths in the chip are all established, the designer carries out operation checking and design rule verification by real wiring length timing simulation considering electric loads of the wires (step 1614).
Then, the designer checks results of the real wiring length timing simulation and the design rule verification, corrects the arrangement made in step 1612 if there is a problem (Step 1616), and returns to step 1614. If there are no problems in step 1611, the designer prepares mask data 1617 of the IC chip by the computer.
Next, a conventional method of designing a base of an FC IC is described with reference to FIG. 32. FIG. 32 is a flowchart showing the conventional method of designing the base of the FC IC. FIG. 32 shows in detail step 3607 of FIG. 31. First, as designing information of each product, a design rule 1601, package information 2602, a customer specification 1603, and circuit information 1607 generated during product designing of FIG. 31 are prepared beforehand.
Then, the designer calculates an area of an internal region based on the customer specification 1603 and the previous circuit information 1607 by using a computer or the like, and also the number of I/O pins (step 1805). Then, the designer calculates a chip size based on the calculated area of the internal region and the calculated number of I/O pins by using the computer or the like (step 1806).
Then, as shown in FIG. 29, based on the package information 1602, the designer collects combinations of an I/O buffer 101, an I/O buffer GND solder ball 113, an I/O buffer power supply solder ball 114, a signal solder ball 115, an I/O buffer GND drawer wire 3216, an I/O buffer power supply drawer wire 3217, and a signal drawer wire 3218 in a group 3453 (step 3707).
At this time, the number of combinations of the I/O buffer 101, the I/O buffer GND solder ball 113, the I/O buffer power supply solder ball 114, the signal solder ball 115, the I/O buffer GND drawer wire 3216, the I/O buffer power supply drawer wire 3217, and the signal drawer wire 3218 varies from product to product, and depends on the customer specification 1603.
Then, the designer checks an impedance characteristic of the signal drawer wire 3218 (step 3708). The designer checks the impedance characteristic (step 3709), and if there is a problem, changes the combination shapes or the number of combinations of the I/O buffer 101, the I/O buffer GND solder ball 113, the I/O buffer power supply solder ball 114, the signal solder ball 115, the I/O buffer GND drawer wire 3216, the I/O buffer power supply drawer wire 3217, and the signal drawer wire 3218 grouped in step 3707. The designer then adjusts the impedance characteristic of the signal drawer wire 3218 (step 3711), and returns to step 3708.
If there are no problems in step 3709, the designer temporarily arranges the group 3453, a RAM 2535, a macrocell and the like on a chip 351 (step 3710). Then, the designer arranges a GND wire and a power supply wire of an internal cell 121 by avoiding the RAM 2535, the macrocell and the like based on power supply wire pitch information of the design rule 1601, connects the GND wire to an internal cell GND solder ball 1033, and the power supply wire to an internal cell power supply solder ball 1134 (step 3712).
Then, the designer makes impedance models of the GND wire and the power supply wire of the internal cell 121 based on a result of the temporary arrangement in step 3710 and a result of the wiring in step 3712 by using the computer or the like (step 3713). Subsequently, the designer estimates a potential reduction based on the prepared circuit models by using a circuit simulator (step 1814).
The designer checks a result of the potential reduction simulation (step 1815). If there is a problem, the designer changes the combination shapes or the number of combinations of the I/O buffer 101, the I/O buffer GND solder ball 113, the I/O buffer power supply solder ball 114, the signal solder ball 115, the I/O buffer GND drawer wire 3216, the I/O buffer power supply drawer wire 3217, and the signal drawer wire 3218 collected in the group, adjusts resistances of the I/O buffer GND drawer wire 3216 and the I/O buffer power drawer wire 3217 (step 3717), and returns to step 3708.
If there are no problems in step 1815, the designer registers information regarding the arrangement of the GND wire and the power supply wire, the arrangement of the group 3453, the pin arrangement or the like on a base database 1608 (step 1816). Accordingly, layout designing of the I/O buffer 101 and the solder balls of the FC IC is finished. In steps thereafter, an FC IC is designed for each product based on the base database 1608. Next, conventional problems are described. First, as shown in FIGS. 27 and 29, in the conventional FC IC, because of a difference in wiring length among the signal drawer wires 3218, skewing (phase shift) occurs among signals of the I/O buffers 101, which results in delay and fluctuation. Thus, a problem of an erroneous operation of the circuit has been inherent.
Especially, in the FC IC of the second conventional example shown in FIG. 29, in the case of the double cross structure of the GND and power supply wires of the plurality of I/O buffers shown in FIG. 30, it is necessary to arrange the I/O buffers adjacently to each other, variance occurs in relative positions of the I/O buffer signal terminal 112 of the I/O buffer 101 and the signal solder ball 115, and a difference in wiring length among the signal drawer wires 3218 becomes larger than that in the first conventional example.
In the conventional FC IC, as shown in FIG. 28, as the signal drawer wire 3218 of the I/O buffer 101 passes on the internal cell 121, parasitic capacitance between the signal drawer wire 3218 of the I/O buffer 101 and the inter-signal wire 229 of the internal cell 121 causes propagation of crosstalk noise, and delay and fluctuation in the internal circuit. Thus, a problem of an erroneous operation of the circuit has been inherent. In particular, following a higher speed of the circuit achieved in recent years, the foregoing problems have become more conspicuous.
In the conventional method of designing the FC IC, the combination of the I/O buffer 101 with the solder balls 113 to 115, 1033 and 1134 depends on a specification of each product, and it is necessary to add the layout information grouping the I/O buffer 101, the solder balls 13 to 115, 10333 and 1134, and the drawer wires 3216 to 3218 to the base database 1608 for product designing. Thus, a problem of longer product design TAT (process days) has been inherent.
If there is a problem with impedance matching or a potential reduction as a result of arranging the group 3453, the GND wire and the power supply wire, it is necessary to adjust or correct the grouped layout information. Thus, the problem of much longer design TAT has been inherent.